The present invention relates generally to integrated circuit devices and, more particularly, to an apparatus and method for implementing an integrated circuit intellectual property (IP) core library architecture.
As the mask costs for manufacturing ASICs (Application Specific Integrated Circuits) increase (e.g., a mask set for a chip is projected to be around 6 to 10 million dollars within the next 10 years), the need to reuse both masks and SOC (System On Chip) designs for multiple customers becomes more and more important. One particular problem associated with the fabrication of an SOC is determining which particular IP core(s) to use in the SOC. By using different IP cores on different customers' chips, the masks used in the formation thereof are, as a result, unique for each customer. Accordingly, a single IP core must therefore be reproduced on a separate mask for each customer.
One existing solution to this problem is to simply populate a chip with some of the basic IP cores required for the SOC and then populate the rest of the chip with FPGA (Field Programmable Logic Array) structures. The remaining IP core functions would then be downloaded into the FPGA to configure the SOC for that particular customer. However, one drawback with respect to this approach is the inefficiency of the FPGA structure in relation to a gate level version of the same IP, as well as the insecurity of the IP cores.
Another possible solution to this problem would be to provide predetermined sets of IP cores that would be treated as a library from a functional point of view, but would be treated as a single block of layout information. However, one problem with this approach lies in the challenge of creating an efficient architecture for the library of IP cores that can handle the requirements of I/O connections, processor bus connections, and irregular shapes of the different kinds of IP cores.
Accordingly, it would be desirable to be able to implement an IP core library architecture in a manner that allows for the unique functional requirements dictated by an customer's desired SOC, but that also reduces mask and verification costs while also providing a practical means of communication between the IP cores, the base or customer logic, and applicable I/O devices.